1. Field of the Invention
The present invention relates to a semiconductor device capable of easily performing a failure analysis even after a silicon wafer is subjected to dicing to provide semiconductor chips.
2. Description of the Related Art
FIG. 11 shows an example of a conventional process from manufacture to shipping of silicon large scale integration (LSI) devices.
According to the process shown in FIG. 11, a wafer process is performed after masks and wafers are separately produced. The wafer process is carried out, as shown in FIG. 12, using a silicon (100) wafer having a diameter of 125 mm and a thickness of 625 .mu.m which has been formed in the wafer manufacturing process shown in FIG. 11. More specifically, circuit elements are formed on the silicon wafer by means of well-known techniques such as oxidation, diffusion, epitaxy, formation of insulating films, formation of electrodes, ion implantation, lithography, cleaning, etc. In most cases, the processes of the oxidation, formation of insulating films, and cleaning are usually performed for each set of 20 to 30 silicon wafers, while the processes of the formation of electrodes, ion implantation, and lithography are carried out for each silicon wafer.
The silicon wafer, which has been subjected to the wafer process, includes a plurality of chips A.sub.1 to A.sub.46, as shown in FIG. 13. Each of the chips is about 1.5.times.1.5 cm.sup.2 in size. As shown in FIG. 11, an electrical test called "probing", that is, a probe test (primary test) is carried out for the silicon wafer. The chips A.sub.1 to A.sub.46 formed on the silicon wafer are separated from one another and then an assembly process is performed to provide connection terminals on these chips. After a packaging process for sealing each of the chips in a package is performed, an electrical test, that is, a secondary test is carried out. Subsequently, a final test, testing the reliability and quality are carried out and semiconductor devices and the devices are shipped after the final test.
In the wafer process described above, when a plurality of silicon wafers are treated at the same time, an unintended variation in the silicon wafers may occur. The variation causes chips, formed from different silicon wafers, to have different characteristics. The different characteristics may result in deterioration of the chips and decrease in the yield. An undesired variation in the same silicon wafer may also occur. Therefore, chips formed from the same silicon wafer have different characteristics, resulting in decrease in yield of devices.
A case where the undesired variation in silicon wafers processed at the same time occur, will be described with reference to FIG. 14. FIG. 14 is a graph whose abscissa shows a position of silicon wafers in a treating apparatus and whose ordinate shows the thickness of gate oxide films of MOSFETs used in the silicon LSI device. As is apparent from FIG. 14, the thickness of the gate oxide films is caused to differ from one another in accordance with the position of the silicon wafers, and at the most 10 percent of variation occurs. Since the thickness of the gate oxide films of the MOSFETs is in proportion to their drive currents, if about 10 percent of variation occurs, the operation speed may be decreased by 10 percent and the power consumption may be increased by 10 percent. The variation is very unfavorable for the devices.
A case where the undesired variation in the same silicon wafer occurs, will be described with reference to FIG. 15. FIG. 15 shows a variation in gate length occurring when the gate electrodes of MOSFETs are etched by means of a well-known reactive anisotropic etching apparatus and, in other words, it shows a deviation from a desired gate length like a contour line. As is apparent from FIG. 15, the size of the gate electrode directly changes the characteristics of the MOSFET. If, for example, the size is large, a logic gate is greatly delayed to deteriorate the performance of devices. Consequently, a large gate electrode is very unfavorable for the device.
It is therefore necessary to analyze the cause of a chip failure due to the undesirable variation, thereby improving the chip failure.
However, the cause of the chip failure due to the variation can be analyzed only by the foregoing probe test, because the probe test is a measurement under the silicon wafer. The chip failure cannot be analyzed after the silicon wafer is diced to provide chips and the chips are packaged. Since the chips simultaneously provided from the silicon wafer have the same structure, it is impossible to specify the position of a chip with a failure in the silicon wafer before the chip is separated from the wafer.
The probe test is directed to sorting defective chips which are not operated at all. Since the final test is carried out after the probe test, electrical characteristics cannot be measured by the probe test in detail. This makes it more difficult to analyze a failure of semiconductor devices.
As described above, conventionally, the unintended variation is caused. That is, the thickness of a thin film, the uniformity of etching, the crystallinity of silicon wafer, the amount of impurity and the like depend the position of the same silicon wafer or different silicon wafers. The chip failure is also caused by the thickness of the thin film, the uniformity of etching, the crystallinity of silicon wafer, the amount of impurity, and the like. In other words, the failure analysis can be made from position information of chips within silicon wafers, and the cause of the failure can be eliminated. However, the failure cannot be analyzed after the wafer is separated into chips.